1. Field of the Invention
The invention generally relates to a manufacturing method of a semiconductor device, more particularly, to a manufacturing method of strip-shaped conductive structures and a non-volatile memory cell.
2. Description of Related Art
Non-volatile memory, due to having advantages in being capable of performing actions, such as data storing, accessing and erasing, for multiple times and not losing the stored data after power failure, has been broadly used in personal computer and electronic equipment.
The non-volatile memory is typically designed as a non-volatile memory cell structure, which includes a tunneling dielectric layer, floating gates, an inter-gate dielectric layer and a control gate that are sequentially disposed on a substrate.
A typical manufacturing process of a non-volatile memory cell structure is to define the non-volatile memory cell structures through a lithography and etching process, after sequentially forming a tunneling dielectric material layer, a floating gate material layer, an inter-gate dielectric material layer and a control gate material layer on a substrate, and to form a plurality of isolation structures between the non-volatile memory cell structures.
However, due to circuit design and application requirements, the non-volatile memory, other than having the non-volatile memory cell structure, further has a logic circuit structure. In terms of manufacturing process, the manufacturing process of the non-volatile memory cell structure has to be integrated with the manufacturing process of the logic circuit structure. Unlike the manufacturing process of the non-volatile memory cell structure, typical manufacturing process of the logic circuit structure will firstly define the isolation structures and an active region in the substrate, wherein top surfaces of the isolation structures will be higher than a top surface of the substrate by a step-high. In order for material layers with similar properties to be used in the non-volatile memory cell structure and the logic circuit structure at the same time, the typical manufacturing process of the logic circuit structure or the like is generally preferred, namely, firstly defining the isolation structures and the active region in the substrate.
However, because the top surfaces of the isolation structures will be higher than the top surface of the substrate when using the typical manufacturing process of the logic circuit structure or the like, the floating gates of the non-volatile memory cell are prone to have sharp corners at the peripheral regions and indentations at the center regions during the subsequent foil ling process of the non-volatile memory cell structure, wherein the sharp corners and the indentations may cause local electric field concentration, and thus when the memory cell executes programming and erasing steps, situations such as power leakage and so forth are liable to occur, thereby resulting in data interpretation errors and other problems, and thus a reliability of the semiconductor device would be affected.